1. Field of Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit coupled on an I/O pad. More particularly, the present invention relates to an ESD circuit on the I/O pad which can prevent a silicon controlled rectifier (SCR) circuit from being latched.
2. Description of Related Art
FIG. 1 is a circuit diagram, illustrating a conventional I/O pad ESD protection circuit. When the voltage from the I/O pad 10 is exported to an internal circuit 12, an ESD protection circuit usually is involved in design to prevent an over voltage from occurring and affecting the operation of the internal circuit 12. In FIG. 1, two transistors 14 and 16 are included in the design. The two transistors 14 and 16 can discharge electrostatic charges away when the over positive voltage or over negative voltage occur on the I/O pad 10. In addition, a low-voltage triggering silicon-controlled rectifier (LVTSCR) 18 is also included, which is used to further enhance the discharge rate.
FIG. 2 is a cross-sectional view, illustrating a conventional semiconductor structure of the LVTSCR. In FIG. 2, a lateral parasitic NPN bipolar junction transistor 30 is formed due to the first N+ doped region 20, the P-type substrate 24, and the second N+ dope region 22. A vertical parasitic PNP bipolar junction transistor 32 is formed due to the doped region 26, the N well 28, and the P-type substrate 24. The base electrodes of these two bipolar junction transistors 28, 30 are respectively driven each other by a collect electrode of bipolar junction transistors, resulting in a positive feedback loop. The positive feedback loop is shown in FIG. 3A as a pnpn diode structure. The pnpn diode structure in FIG. 3A has I-V curves as shown in FIG. 3B. In FIG. 3B, IH is the minimum working current to active the pnpn diode. When I>IH, a latch-up would occur, causing the function of the ESD protection circuit to be temporarily or permanently failure. With respect to FIG. 2, when the voltage applied on the I/O pad 10 has an instant over voltage or over current, it then causes the latch-up on the SCR structure, resulting in failure of the ESD protection circuit.